Proper clock functionality and performance are essential for SoC operation. Static timing analysis (STA) tools have served well for verifying...
EDA
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Remember the days when verification meant running a simulator with directed tests? (Back then we just called them tests.) Then...
My first transistor-level IC design job was with Intel, doing DRAM designs by shrinking the layout to a smaller process...
Just prior to this year’s Synopsys User Group (SNUG) meeting, I had a call with Hany Elhak, Group Director of...
Rich Weber co-founded Semifore in 2006 with Jamsheed Agahi. Rich has a long history of complex chip and system design...
It would be nice if there were a pre-packaged set of assertions which could formally check all aspects of cache...
Agile methods in hardware design are becoming topical again. What does this mean for verification? Paul Cunningham (GM, Verification at...
I read the semiconductor press, LinkedIn and social media (Twitter, Facebook) every morning along with an RSS feed that I...
SoC integration offers huge benefits through reduced chip count in finished systems, higher performance, improved reliability, etc. A single die...
In business we all have heard the maxim, “Time is Money.” I learned this lesson early on in my semiconductor...
